Glossary entry (derived from question below)
English term or phrase:
timing closure
French translation:
respect des contraintes temporelles
Added to glossary by
Lany Chabot-Laroche
Apr 20, 2010 22:03
14 yrs ago
1 viewer *
English term
Canada
timing closure
English to French
Tech/Engineering
Telecom(munications)
The customer now easily meets their timing objectives with every build and was introduced to a new flow that speeds up the timing closure process significantly.
Processus d'un fabricant qu'équipement de télécommunication.
Processus d'un fabricant qu'équipement de télécommunication.
Proposed translations
(French)
| 3 | respect des contraintes temporelles |
Arnold T.
|
Proposed translations
14 mins
Selected
respect des contraintes temporelles
En Anglais :
http://www.wipo.int/pctdb/en/wo.jsp?IA=WO2004111667&DISPLAY=...
"TIMING CLOSURE MONITORING CIRCUIT AND METHOD"
En Français :
http://www.wipo.int/pctdb/fr/wo.jsp?IA=WO2004111667&DISPLAY=...
"CIRCUIT DE SURVEILLANCE DU RESPECT DES CONTRAINTES TEMPORELLES ET PROCEDE CORRESPONDANT"
--------------------------------------------------
Note added at 15 mins (2010-04-20 22:19:10 GMT)
--------------------------------------------------
Explications :
http://en.wikipedia.org/wiki/Timing_closure
"Timing closure is the process by which an FPGA or a VLSI design is modified to meet its timing requirements. Most of the modifications are handled by EDA tools based on directives given by a designer. The term is also used for the goal that is achieved, when such a design has reached the end of the flow and its timing requirements are satisfied.
The main steps of the design flow, which may be involved in this process, are logic synthesis, placement, clock-tree synthesis and routing. With present technologies all of them need to be timing-aware for a design to properly meet its timing requirements, but with technologies in the range of the micrometre only logic synthesis EDA tools had such a prerequisite.
Nevertheless, even if timing-awareness was extended to all these steps starting from well-established principles used for logic synthesis, the two phases, logic and physical, of the timing closure process are conventionally handled by different design teams and different EDA tools. Design Compiler by Synopsys, Encounter RTL Compiler by Cadence Design Systems and BlastCreate by Magma Design Automation are examples of logic synthesis tools. IC Compiler by Synopsys, SoC Encounter by Cadence Design Systems and Blast Fusion by Magma Design Automation are examples of tools capable of timing-aware placement, clock tree synthesis and routing and therefore used for physical timing closure.
A timing requirement needs to be translated into a static timing constraint for an EDA tool to be able to handle it."
--------------------------------------------------
Note added at 16 hrs (2010-04-21 14:37:14 GMT)
--------------------------------------------------
Le sens : "Accélérer les/la procédure(s) pour respecter les contraintes temporelles ..." !
--------------------------------------------------
Note added at 6 days (2010-04-27 09:26:07 GMT) Post-grading
--------------------------------------------------
Merci Lany !
http://www.wipo.int/pctdb/en/wo.jsp?IA=WO2004111667&DISPLAY=...
"TIMING CLOSURE MONITORING CIRCUIT AND METHOD"
En Français :
http://www.wipo.int/pctdb/fr/wo.jsp?IA=WO2004111667&DISPLAY=...
"CIRCUIT DE SURVEILLANCE DU RESPECT DES CONTRAINTES TEMPORELLES ET PROCEDE CORRESPONDANT"
--------------------------------------------------
Note added at 15 mins (2010-04-20 22:19:10 GMT)
--------------------------------------------------
Explications :
http://en.wikipedia.org/wiki/Timing_closure
"Timing closure is the process by which an FPGA or a VLSI design is modified to meet its timing requirements. Most of the modifications are handled by EDA tools based on directives given by a designer. The term is also used for the goal that is achieved, when such a design has reached the end of the flow and its timing requirements are satisfied.
The main steps of the design flow, which may be involved in this process, are logic synthesis, placement, clock-tree synthesis and routing. With present technologies all of them need to be timing-aware for a design to properly meet its timing requirements, but with technologies in the range of the micrometre only logic synthesis EDA tools had such a prerequisite.
Nevertheless, even if timing-awareness was extended to all these steps starting from well-established principles used for logic synthesis, the two phases, logic and physical, of the timing closure process are conventionally handled by different design teams and different EDA tools. Design Compiler by Synopsys, Encounter RTL Compiler by Cadence Design Systems and BlastCreate by Magma Design Automation are examples of logic synthesis tools. IC Compiler by Synopsys, SoC Encounter by Cadence Design Systems and Blast Fusion by Magma Design Automation are examples of tools capable of timing-aware placement, clock tree synthesis and routing and therefore used for physical timing closure.
A timing requirement needs to be translated into a static timing constraint for an EDA tool to be able to handle it."
--------------------------------------------------
Note added at 16 hrs (2010-04-21 14:37:14 GMT)
--------------------------------------------------
Le sens : "Accélérer les/la procédure(s) pour respecter les contraintes temporelles ..." !
--------------------------------------------------
Note added at 6 days (2010-04-27 09:26:07 GMT) Post-grading
--------------------------------------------------
Merci Lany !
3 KudoZ points awarded for this answer.
Something went wrong...